1. Field of the Invention
The present invention generally pertains to a nonvolatile semiconductor memory device of a split-gate type, such as EEPROM (electrically erasable programmable read only memory), flash memory, EPROM, or the like, and a method for manufacturing such a memory device as well.
2. Description of the Related Art
Conventional nonvolatile semiconductor memory devices of the aforesaid type are known, for example, from Japanese Laid-Open Patent Application No. Hei 2-110981, which describes an EEPROM. As depicted in FIG. 1, the conventional EEPROM described therein comprises a P-type silicon substrate 601, a P.sup.+ diffusion layer (P-type impurity diffusion layer) 602 defining a channel region, a gate oxide 603, a floating gate 604, N.sup.+ diffusion layers (N-type impurity diffusion layers) 607 and 607 each defining a source or drain region serving as a virtual ground, an interlayer dielectric 608, a control gate 609, and a split gate SG.
In the P-type semiconductor substrate 601, the P.sup.+ diffusion layer (channel) 602 disposed between the N.sup.+ diffusion layers (source and drain) 607 and 607 comprises an area covered with the floating gate 604 and an area uncovered therewith, the latter defining the split gate SG. Despite the amount of the electric charges present in the floating gate 604, the electric current flowing this split gate SG can be controlled by the voltage applied to the control gate 609. Accordingly, even if the electrons present in the floating gate 604 are released excessively to induce a depletion state in that part of the P.sup.+ diffusion layer (channel) 602 disposed underneath the floating gate 604, since the electric current can be cut off at a site of the split gate SG, the erroneous working of the EEPROM can be prevented. Thus, with the provision of the split gate SG, it is possible to achieve an increased reliability for EEPROM.
Referring to FIGS. 2(a) to 2(f), each of the steps for the manufacturing method of the aforesaid EEPROM will now be described. First, a P-type impurity diffusion layer (P.sup.+ diffusion layer) 602 having an impurity concentration greater than that of a P-type silicon substrate 601 is formed on the channel area of the silicon substrate 601 with a gate oxide (thermal oxide film) 603 formed thereon (FIG. 2(a)), and then a patterning is effected for the floating gate 604 (FIG. 2(b)). Subsequently, after causing oxide to deposit on the P-type silicon substrate 601, etching-back is effected by means of anisotropic etching to form oxide side walls 605 on the opposite sides of each of the floating gates 604 (FIG. 2(c)). Thereafter, among the oxide side walls 605 formed on the opposite sides of each floating gate 604, only one of the side walls situated on one side (left side in FIG. 2(d)) is covered with photoresist 606 (FIG. 2(d)), and the exposed oxide side wall 605 on the other side (right side in FIG. 2(d)) is removed by etching.
Then, ions of N-type impurity such as arsenic (As) are implanted while permitting the floating gates 604 and the oxide side walls 605 to serve as self-aligning masks, to thereby form N.sup.+ diffusion layers 607 and 607 serving as source and drain regions (FIG. 2(e)). Further, after the removal of the oxide side walls 605, thin interlayer dielectric 608 is deposited on the P-type silicon substrate 601, and control gates 609 are formed (FIG. 2(f)). An EEPROM is thus manufactured. In this method, the split gate is formed by a self-alignment process as described above. Accordingly, a high-precision split gate can be obtained.
In the conventional art as described above, however, inasmuch as the split areas are formed in a self-aligning manner by forming oxide side walls 605 on the opposite sides of a respective floating gate 604, the manufacturing process is complicated, with an increased number of steps required, resulting in lowering of yield and inflation of cost, although a sufficient precision can be achieved.
Furthermore, in the conventional art, since it is necessary to have a margin taking into consideration an alignment precision error in the photolithography step in order to protect only one of the opposite oxide side walls 605, micronization is difficult. Moreover, also in the step of forming the P.sup.+ diffusion layer 602 only in the channel region of the P-type silicon substrate 601, since it is necessary to have a margin taking into consideration an alignment precision error in the photolithography step, micronization is difficult. Therefore, with the conventional art described in the aforesaid document, larger integration cannot be attained.